1. Field of the Invention
The present invention relates to a built-in self-test circuit (BIST circuit), and more particularly, to a memory built-in self-test (MBIST) circuit and its address counter and clock switching circuit.
2. Description of Related Art
Along with the advance of semiconductor industry, the semiconductor process has stepped in very deep sub-micro (VDSM) technique level, where a more complicate and more precision chip design is required. Most products require embedded memories to handle complex and various operations, which accordingly needs tremendous test patterns for memory testing. Considering the above-mentioned need, in particular, the connection difficulty between a great lot of input/output ports of the memories and the external circuit out of the chip, a new technique, named as memory built-in self-test circuit, was provided. By using MBIST technique, a circuit purposely built in a memory chip is utilized to perform reading/writing tests in a specific duration on the internal memory circuits so as to judge the quality of the memory chip.
In a conventional MBIST circuit, several algorithms are usually supported, such as checkerboard algorithm, march C+ algorithm and march C− algorithm The checkerboard algorithm is to write alternately logic level values ‘1’ and ‘0’ into adjacent bits on the physical cell positions of a memory under test, followed by reading the hexadecimal values, for example 55 or AA etc. for testing. While with a march C+ algorithm or a march C− algorithm, the reading/writing tests are performed in an increasing transition order of addresses or a decreasing transition order of addresses on the memory bits repeatedly, until the predetermined test iterations are satisfied. A conventional MBIST is usually generated by electronic design automation (EDA) software, which has a fixed format and cannot be changed to suit the specific demand of user. For example, in the applications to test some application-specific integrated circuits (ASICs), the conventional MBIST is unable to provide an appropriate test pattern so as to lower the test fault coverage. Furthermore, when a user needs some specific test patterns for a diagnosis purpose, the EDA software fails to accomplish the goal as well. Although a MBIST able to accept a programming done by user is available today, but the area occupied by the above-mentioned built-in self-test circuit is still not compact sufficiently to satisfy the modern semiconductor industry for less circuit area and cheaper cost.
Additionally, in a conventional MBIST capable of supporting both schemes of generating memory addresses by column scanning and row scanning, two sets of counters are needed. FIG. 1 is a diagram of a conventional address counter, wherein the address counter includes a column scan counter 120, a row scan counter 110, an address register 130 and a multiplexer 140. The column scan counter 120 is used as an address counter during performing a column scan test, while the row scan counter 110 is used during performing a row scan test. When column scan is enabled (i.e., row scan is disabled), the multiplexer 140 selects a column scan address line 102 sent to the address register 130. In contrast, when row scan is enabled (i.e., column scan is disabled), the multiplexer 140 selects a row scan address line 101 sent to the address register 130. Once the memory under test has a large size, the corresponding bit number of address increases accordingly, which results in a large portion of the chip area occupied by the column scan counter 120 and the row scan counter 110. The production cost increases as well.
Another difficulty a conventional MBIST encounters rests in that the available clock frequency provided by a modern auto-testing equipment (ATE) is far lower than the clock frequency of a MBIST circuit, so that a clock hazard may occur during clock switching between a self-test mode and an external test mode with the ATE. The clock hazard may cause unexpected event during the subsequent test operations, which leads to faulty operation or no operation and increases the test difficulty.